An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to the gate on which sidewall spacers have been formed. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or Ldd) at the edge near the channel. The second heavier dose forms a low resistivity heavily doped region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. The lightly doped region is not necessary for the source (unless bidirectional current is used), however lightly doped regions are typically formed for both the source and drain to avoid additional processing steps.
Including a heavily doped portion and a lightly doped portion in a source or drain is referred to as having graded doping within the source and drain. MOSFETs without graded doping generally have a shortened life which is well below the industry-wide design point of a 10-year life. To extend the life of an IGFET, a drain with a graded, or lightly doped extension is produced. Due to processing steps, a graded source is also produced. Qualitatively, .epsilon..sub.ymax is reduced by such a graded or lightly doped extension or buffer region because the maximum electric field in a reverse-biased pn junction is highest when the junction is abrupt. By replacing the abrupt drain doping profile of a conventional IGFET with a drain that has a more gradually decreasing lateral doping profile (i.e., a graded drain), the voltage drop becomes shared by the drain and the channel, in contrast to an abrupt n.sup.+ /p drain junction, in which almost the entire voltage drop occurs across the lightly doped (channel) side of the junction. The model equation for .epsilon..sub.ymax is provided below: EQU .epsilon..sub.ymax =(V.sub.DS -V.sub.DSsat)/l (Equation 1)
where, .epsilon..sub.ymax is the maximum channel electric field, l is the channel length, V.sub.DS is the voltage across the channel and V.sub.DSsat is the voltage across the channel at saturation. .epsilon..sub.ymax is significantly reduced by the presence of such a lightly doped region because this is another way to increase the denominator of Equation 1.
Graded-drain regions can be created in IGFETs in a number of ways, including: (1) using phosphorus in place of As as the dopant of the source/drain regions; (2) adding fast diffusing phosphorus to an As-doped drain region, and driving the phosphorus laterally ahead of the arsenic with a high temperature diffusion step to create a double-diffused drain [DDD] structure; and (c) pulling the highly doped (n.sup.+) drain region away from the gate edge with an "oxide spacer" to create a lightly doped drain (LDD) structure.
Each of these methods requires a number of processing steps. A method is needed which reduces the number of processing steps. The formation of spacers by the deposition and etch method is one subprocess that requires many steps.